Rainbow-electronics AT89LS51 Manual de usuario Pagina 1

1Features• Compatible with MCS-51®Products• 4K Bytes of In-System Programmable (ISP) Flash Memory– Endurance: 1000 Write/Erase Cycles• 2.7V to 4.0V Op

10AT89LS513053A–8051–05/02.Figure 1. Interrupt SourcesTable 4. Interrupt Enable (IE) Register(MSB) (LSB)EA – – ES ET1 EX1 ET0 EX0Enable Bit = 1 enable

11AT89LS513053A–8051–05/02OscillatorCharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can beconfig

12AT89LS513053A–8051–05/02ProgramMemory LockBitsThe AT89LS51 has three lock bits that can be left unprogrammed (U) or can be programmed(P) to obtain t

13AT89LS513053A–8051–05/02Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY out-put signal. P3.0 is pulled low after A

14AT89LS513053A–8051–05/02Power-off sequence (if needed):Set XTAL1 to “L” (if a crystal is not used).Set RST to “L”.Turn VCCpower off.DataPolling: The

15AT89LS513053A–8051–05/02Figure 4. Programming the Flash Memory (Parallel Mode)Figure 5. Verifying the Flash Memory (Parallel Mode)P1.0-P1.7P2.6P3.6P

16AT89LS513053A–8051–05/02Figure 6. Flash Programming and Verification Waveforms – Parallel ModeFlash Programming and Verification Characteristics (Pa

17AT89LS513053A–8051–05/02Figure 7. Flash Memory Serial DownloadingFlash Programming and Verification Waveforms – Serial ModeFigure 8. Serial Programm

18AT89LS513053A–8051–05/02Note: 1. B1 = 0, B2 = 0 → Mode 1, no lock protectionB1 = 0, B2 = 1→ Mode 2, lock bit 1 activatedB1 = 1, B2 = 0→ Mode 3, lock

19AT89LS513053A–8051–05/02Serial Programming CharacteristicsFigure 9. Serial Programming TimingMOSIMISOSCKtOVSHtSHSLtSLSHtSHOXtSLIVTable 9. Serial Pro

2AT89LS513053A–8051–05/02Pin ConfigurationsPDIPTQFP12345678910111213141516171819204039383736353433323130292827262524232221 P1.0 P1.1P1.2P1.3P1.4(MOSI)

20AT89LS513053A–8051–05/02Notes: 1. Under steady state (non-transient) conditions, IOLmust be externally limited as follows:Maximum IOLperportpin:10mA

21AT89LS513053A–8051–05/02AC CharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for

22AT89LS513053A–8051–05/02External Program Memory Read CycleExternal Data Memory Read CycletLHLLtLLIVtPLIVtLLAXtPXIZtPLPHtPLAZtPXAVtAVLLtLLPLtAVIVtPXI

23AT89LS513053A–8051–05/02External Data Memory Write CycleExternal Clock Drive WaveformstLHLLtLLWLtLLAXtWHLHtAVLLtWLWHtAVWLtQVWXtQVWHtWHQXA0 - A7 F

24AT89LS513053A–8051–05/02Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC-

25AT89LS513053A–8051–05/02Ordering InformationSpeed(MHz)PowerSupply Ordering Code Package Operation Range16 2.7V to 4.0V AT89LS51-16ACAT89LS51-16JCAT8

26AT89LS513053A–8051–05/02Packaging Information44A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 mm Bo

27AT89LS513053A–8051–05/0244J–PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold

28AT89LS513053A–8051–05/0240P6 – PDIP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 40P6, 40-lead (0.600"/15.24 mm Wide) Plast

Printed on recycled paper.3053A–8051–05/02 xM© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than thos

3AT89LS513053A–8051–05/02Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7FLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDU

4AT89LS513053A–8051–05/02Pin DescriptionVCC Supply voltage.GND Ground.Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port,

5AT89LS513053A–8051–05/02RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets thedevice. This pin drives

6AT89LS513053A–8051–05/02SpecialFunctionRegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shownin Table 1.

7AT89LS513053A–8051–05/02User software should not write 1s to these unlisted locations, since they may be used in futureproducts to invoke new feature

8AT89LS513053A–8051–05/02Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR.POF is set to “1” during power up. It c

9AT89LS513053A–8051–05/02pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, itshould be serviced in those sections of code