Rainbow-electronics ADC08062 Manual de usuario descargar pdf (Pagina 3)

AC Electrical Characteristics

The following specifications apply for V

a

e

5V, t

r

e

t

f

e

10 ns, V

REF

a

e

5V, V

REF

b

e

0V unless otherwise specified.

Boldface limits apply for T

A

e

T

J

e

T

MIN

to T

MAX

; all other limits T

A

e

T

J

e

25

§

C.

Symbol Parameter Condition

(Note 7)

Typical

AD08061 and

ADC08061CMJ

(Limit)

Units

ADC08062 with BIN,

BIWM, CIN and

CIWM suffixes

Limits (Limit)

(Note 8) (Note 8)

t

WR

Write Time Mode Pin to V

a

;

100 100 100 ns (min)

(

Figures 2a, 2b,

and

3

)

t

RD

Read Time (Time from Falling Edge Mode Pin to V

a

;

(Figure 2a)

350 350 515 ns (min)

of WR

to Falling Edge of RD)

t

RDW

RD

Width Mode Pin to GND;

(Figure 4)

200 250 250 ns (min)

400 400 400 ns (max)

t

CONV

WR-RD Mode Conversion Time Mode Pin to V

a

;

(Figure 2a)

500 560 790 ns (max)

(t

WR

a

t

RD

a

t

ACC1

)

t

CRD

RD Mode Conversion Time Mode Pin to GND;

(Figure 1)

655 900 940 ns (max)

t

ACCO

Access Time (Delay from Falling C

L

s

100 pF

640 900 940 ns (max)

Edge of RD

to Output Valid) Mode Pin to GND;

(Figure 1)

t

ACC1

Access Time (Delay from C

L

s

10 pF 45

110 175 ns (max)

Falling Edge C

L

e

100 pF 50

of RD

to Output Valid) Mode Pin to V

a

,t

RD

s

t

INTL

(Figure 2a)

t

ACC2

Access Time (Delay from C

L

s

10 pF 25

55 60 ns (max)

Falling Edge C

L

e

100 pF 30

of RD

to Output Valid) t

RD

l

t

INTL

;(

Figures 2b

and

4

)

t

0H

TRI-STATE

É

Control (Delay from R

L

e

3kX,C

L

e

10 pF

30 60 60 ns (max)

Rising Edge of RD

to HI-Z State)

t

1H

TRI-STATE Control (Delay from R

L

e

3kX,C

L

e

10 pF

30 60 60 ns (max)

Rising Edge of RD to HI-Z State)

t

INTL

Delay from Rising Edge of (

Figures 2b,

and

3

)

520 690 690 ns (max)

WR

to Falling Edge of INT Mode Pin

e

V

a

,C

L

e

50 pF

t

INTH

Delay from Rising Edge of C

L

e

50 pF; (

Figures 1, 2a,

50 95 100 ns (max)

RD

to Rising Edge of INT

2b, and 4

)

t

INTH

Delay from Rising Edge of C

L

e

50 pF;

(Figure 3)

45 95 100 ns (max)

WR

to Rising Edge of INT

t

RDY

Delay from CS to RDY Mode Pin

e

0V, C

L

e

50 pF,

25 45 50 ns (max)

R

L

e

3kX

(Figure 1)

t

ID

Delay from INT to Output Valid R

L

e

3kX,C

L

e

100 pF; 0

15 15 ns (max)

(Figure 3)

t

RI

Delay from RD to INT Mode Pin

e

V

a

,t

RD

s

t

INTL

;

60 115 175 ns (max)

(Figure 2a)

t

N

Time between End of RD (

Figures 1, 2a, 2b, 3

and

4

)

50 50 50 ns (min)

and Start of New Conversion

t

AH

Channel Address Hold Time (

Figures 1, 2a, 2b, 3

and

4

)10 60 60 ns (min)

t

AS

Channel Address Setup Time (

Figures 1, 2a, 2b, 3

and

4

)0 00ns (max)

t

CSS

CS Setup Time (

Figures 1, 2a, 2b, 3

and

4

)0 00ns (max)

t

CSH

CS Hold Time (

Figures 1, 2a, 2b, 3

and

4

)0 00ns (min)

C

VIN

Analog Input Capacitance 25 pF

C

OUT

Logic Output Capacitance 5 pF

C

IN

Logic Input Capacitance 5 pF

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