
3
ATtiny15L
1187E–AVR–06/02
Block Diagram Figure 1. The ATtiny15L Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLA
TOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
HARDWARE
STACK
MCU CONTROL
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
INSTRUCTION
DECODER
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PROGRAMMING
LOGIC
TIMING AND
CONTROL
TIMER/
COUNTER1
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORT B DRIVERS
PB0-PB5
VCC
GND
CONTROL
LINES
+
-
ANALOG
COMPARATOR
8-BIT DATA BUS
Z
ISP MODULE
INTERRUPT
UNIT
DATA
EEPROM
INTERNAL
OSCILLA
TOR
TUNABLE
ANALOG MUX ADC
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