
MAX9257/MAX9258
______________________________________________________________________________________ 17
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
FIRST BIT
SDI
PCLK_OUT
DOUT,
HSYNC_OUT,
VSYNC_OUT
LAST BIT
SERIAL WORD N
SERIAL-WORD LENGTH
SERIAL WORD N+1 SERIAL WORD N+2
t
SPD1
PARALLEL WORD N-2
PARALLEL WORD N-1 PARALLEL WORD N
NOTE: PCLK_OUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 14. MAX9258 Serial-to-Parallel Delay
1.0UI0.75UI0.50UI0.25UI0.0UI
t
JT
t
S
t
S
t
JT
+25mV
-25mV
+100mV
0V
-100mV
INPUT TEMPLATE FOR LVDS SERIAL
V
SDI+
- V
SDI-
NOTE: UI IS ONE SERIAL BIT. TIME INPUT IS MEASURED DIFFERENTIALLY (V
SDI+
- V
SDI-
).
t
R1A
t
F1B
t
R1B
t
F1A
(SDO+) - (SDO-)
0.8V
OD(+)
t
F2
t
R2
0.8 x | V
OD(+)
+ V
OD(-)
| 0.8 x | V
OD(+)
+ V
OD(-)
|
0.2V
OD(-)
0.8V
OD(-)
0.2V
OD(-)
0.8V
OD(-)
0.2 x | V
OD(+)
+ V
OD(-)
| 0.2 x | V
OD(+)
+ V
OD(-)
|
1 0
0.2V
OD(+)
0.8V
OD(+)
0.2V
OD(+)
Figure 15. MAX9258 Jitter Tolerance
Figure 16. Control Channel Transition Time
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