
MAX8759
Low-Cost, SMBus, CCFL Backlight Controller
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
BATT
= 12V, V
CC
= V
DD,
T
A
= -40°C to +85°C.) (Note 1)
MIN TYP MAX
PWMI Input Low Voltage 0.7 V
PWMI Input High Voltage 2.1 V
PWMI Input Frequency Range 5 50 kHz
PWMI duty cycle = 100% 98
PWMI duty cycle = 50% 48 52PWMI Brightness Setting
PWMI duty cycle = 0% 9.7
10.3
%
ALS Full-Adjustment Range 0 1.8 V
VALS Output Voltage
MAX8759 is enabled, 6V < V
BATT
< 28V,
I
LOAD
= 1mA
5.10 5.50
V
VALS On-Resistance MAX8759 is enabled 60 Ω
V
BATT
= 9V, R
THR
= 100kΩ 0 0.3
Zero-Crossing Delay
V
BATT
= 12V, R
THR
= 100kΩ
1.50 2.10
µs
Maximum Zero-Crossing Delay V
BATT
= 16V, R
THR
= 100kΩ 3.2 4.4 µs
DEL rising 4.5
DEL Disable Threshold
DEL falling 3.9
V
V
ISEC
< 1.25V and V
IFB
< 540mV; V
FLT
= 2V
V
ISEC
< 1.25V and V
IFB
> 660mV; V
FLT
= 2V -1.5 -0.8
V
ISEC
> 1.25V and V
IFB
> 660mV; V
FLT
= 2V
115 155
µA
TFLT Trip Threshold Rising edge 3.7 4.3 V
SDA, SCL, Input Low Voltage 0.7 V
SDA, SCL, Input High Voltage 2.1 V
SDA Output Low-Sink Current V
SDA
= 0.4V 4 mA
SMBus Frequency 10 100 kHz
SMBus Free Time t
BUF
4.7 µs
SCL Serial Clock High Period t
HIGH
4µs
SCL Serial Clock Low Period t
LOW
4.7 µs
START Condition Setup Time t
SU:STA
4.7 µs
START Condition Hold Time t
HD:STA
4µs
STOP Condition Setup Time from SCL t
SU:STO
4µs
SDA Valid to SCL Rising-Edge Setup Time,
Slave Clocking in Data
t
SU:DAT
250 ns
SCL Falling Edge to SDA Transition t
HD:DAT
0ns
SCL Falling Edge to SDA Valid,
Reading Out Data
t
DV
200 ns
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
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