Rainbow-electronics MAX6965 Manual de usuario Pagina 4

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MAX6965
9-Output LED Driver with Intensity Control
4 _______________________________________________________________________________________
PORT OUTPUT LOW VOLTAGE WITH 50mA
LOAD CURRENT vs. TEMPERATURE
PORT OUTPUT LOW VOLTAGE V
OL
(V)
0.1
0.2
0.3
0.4
0.5
0.6
0
MAX6965 toc04
TEMPERATURE (°C)
1109565 80-10 5 20 35 50-25-40 125
V+ = 3.6V
V+ = 2.7V
V+ = 2V
PORT OUTPUT LOW VOLTAGE WITH 20mA
LOAD CURRENT vs. TEMPERATURE
MAX6965 toc05
TEMPERATURE (°C)
PORT OUTPUT LOW VOLTAGE V
OL
(V)
1109580655035205-10-25
0.1
0.2
0.3
0.4
0.5
0.6
0
-40 125
ALL OUTPUTS LOADED
V+ = 3.6V
V+ = 2.7V
V+ = 2V
PWM CLOCK FREQUENCY
vs. TEMPERATURE
MAX6965 toc06
TEMPERATURE (°C)
PWM CLOCK FREQUENCY
1109580655035205-10-25
0.925
0.950
0.975
1.000
1.025
1.050
0.900
-40 125
V+ = 3.6V
V+ = 2V
V+ = 2.7V
NORMALIZED TO V+ = 3.3V, T
A
= +25°C
STANDBY CURRENT vs. TEMPERATURE
MAX6965 toc01
TEMPERATURE (°C)
STANDBY CURRENT (µA)
1109565 80-10 5 20 35 50-25
1
2
3
4
5
6
7
8
9
10
0
-40 125
V+ = 3.6V
PWM ENABLED
V+ = 2.7V
PWM ENABLED
V+ = 2V
PWM DISABLED
V+ = 2.7V
PWM DISABLED
V+ = 3.6V
PWM
DISABLED
V+ = 2V
PWM ENABLED
SUPPLY CURRENT vs. TEMPERATURE
(PWM DISABLED; f
SCL
= 400kHz)
MAX6965 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
1109565 80-10 5 20 35 50-25
10
20
30
40
50
60
70
0
-40 125
V+ = 3.6V
V+ = 2.7V
V+ = 2V
5
10
15
20
25
30
35
40
45
50
55
60
65
70
0
SUPPLY CURRENT vs. TEMPERATURE
(PWM ENABLED; f
SCL
= 400kHz)
MAX6965 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
1109565 80-10 5 20 35 50-25-40 125
V+ = 3.6V
V+ = 2.7V
V+ = 2V
__________________________________________Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
TIMING CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2V to 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, T
A
= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RST Pulse Width t
W
s
Output Data Valid t
DV
Figure 10 5 µs
Note 1: All parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCLs falling edge.
Note 3: Guaranteed by design.
Note 4: C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
DD
and 0.7 x V
DD
.
Note 5: I
SINK
6mA. C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 x V
DD
and 0.7 x V
DD
.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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