Rainbow-electronics MAX3107 Manual de usuario descargar pdf (Pagina 41)

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MAX3107

SPI/I

C UART with 128-Word FIFOs

and Internal Oscillator

Bits 7 and 6: PLLFactor[1:0]

The two PLLFactor[1:0] bits allow programming with select PLL’s multiplication factor. The input and output frequencies

of the PLL have to be limited to the ranges shown in Table 4. Enable the PLL through CLKSource[2].

Bits 5–0: PreDiv[5:0]

The six PreDiv[5:0] bits allow programming the divisor of the PLL’s predivider. The divisor must be chosen such that

the output frequency of the predivider, which equals the PLL’s input frequency, is limited to the ranges shown in Table 4.

The output frequency of the internal oscillator or the input frequency of XIN is f

CLK;

PLLIN

= f

CLK

/PreDiv (Figure 4).

PreDiv is an integer that must be in the range of 1 to 63.

PLLConfig—PLL Configuration Register

Table 4. PLLFactor[1:0] Selection Guide

Figure 14. PLL Signal Path

PREDIVIDER

CLK

PLL

PLLIN

REF

FRACTIONAL

BAUD-RATE

GENERATOR

ADDRESS: 0x1A

MODE: R/W

BIT 7 6 5 4 3 2 1 0

NAME

PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0

RESET

0 0 0 0 0 0 0 1

PLLFactor1 PLLFactor0

MULTIPLICATION

FACTOR

PLLIN

REF

MIN MAX MIN MAX

0 0 6 500kHz 800kHz 3MHz 4.8MHz

0 1 48 850kHz 1.2MHz 40.8MHz 56MHz

1 0 96 425kHz 1MHz 40.8MHz 96MHz

1 1 144 390kHz 667kHz 56MHz 96MHz

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 50 51

C UART with 128-Word FIFOs 1

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