Rainbow-electronics AT45DB041D Manual de usuario

Features• Single 2.5V or 2.7V to 3.6V Supply• RapidSTMSerial Interface: 66MHz Maximum Clock Frequency– SPI Compatible Modes 0 and 3• User Configurable

103595R–DFLASH–11/2012AT45DB041D7.6 Sector EraseThe Sector Erase command can be used to individually erase any sector in the main memory.There are eig

113595R–DFLASH–11/2012AT45DB041DThe WP pin can be asserted while the device is erasing, but protection will not be activated untilthe internal erase c

123595R–DFLASH–11/2012AT45DB041D8.1 Software Sector Protection8.1.1 Enable Sector Protection CommandSectors specified for protection in the Sector Pro

133595R–DFLASH–11/2012AT45DB041DIf the device is power cycled, then the software controlled protection will be disabled. Once thedevice is powered up,

143595R–DFLASH–11/2012AT45DB041D9.1 Sector Protection RegisterThe nonvolatile Sector Protection Register specifies which sectors are to be protected o

153595R–DFLASH–11/2012AT45DB041DTable 9-4. Erase Sector ProtectionFigure 9-2. Erase Sector Protection Register9.1.2 Program Sector Protection Register

163595R–DFLASH–11/2012AT45DB041DTable 9-5. Program Sector Protection Register CommandFigure 9-3. Program Sector Protection Register9.1.3 Read Sector P

173595R–DFLASH–11/2012AT45DB041D10. Security Features10.1 Sector LockdownThe device incorporates a Sector Lockdown mechanism that allows each individu

183595R–DFLASH–11/2012AT45DB041D10.1.1 Sector Lockdown RegisterSector Lockdown Register is a nonvolatile register that contains 16-bytes of data, as s

193595R–DFLASH–11/2012AT45DB041D10.2 Security RegisterThe device contains a specialized Security Register that can be used for purposes such asunique

23595R–DFLASH–11/2012AT45DB041Dreduces active pin count, facilitates hardware layout, increases system reliability, minimizesswitching noise, and redu

203595R–DFLASH–11/2012AT45DB041D10.2.2 Reading the Security RegisterThe Security Register can be read by first asserting the CS pin and then clocking

213595R–DFLASH–11/2012AT45DB041DOn completion of the compare operation, bit six of the status register is updated with the result ofthe compare.11.3 A

223595R–DFLASH–11/2012AT45DB041DThe result of the most recent Main Memory Page to Buffer Compare operation is indicated usingbit six of the status reg

233595R–DFLASH–11/2012AT45DB041D12.1 Resume from Deep Power-downThe Resume from Deep Power-down command takes the device out of the Deep Power-downmod

243595R–DFLASH–11/2012AT45DB041D13.1 Programming the Configuration RegisterTo program the Configuration Register for “power of 2” binary page size, th

253595R–DFLASH–11/2012AT45DB041D14.1 Manufacturer and Device ID InformationNote: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be

263595R–DFLASH–11/2012AT45DB041D14.2 Operation Mode SummaryThe commands described previously can be grouped into four different categories to betterde

273595R–DFLASH–11/2012AT45DB041D15. Command TablesTable 15-1. Read CommandsCommand OpcodeMain Memory Page Read D2HContinuous Array Read (Legacy Comman

283595R–DFLASH–11/2012AT45DB041DNote: 1. These legacy commands are not recommended for new designs.Read Sector Lockdown Register 35HProgram Security R

293595R–DFLASH–11/2012AT45DB041DNotes: x = Don’t CareTable 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256-Bytes)Page Size = 25

33595R–DFLASH–11/2012AT45DB041DNote: 1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND

303595R–DFLASH–11/2012AT45DB041DNotes: P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t CareTable 15-7. Detailed Bit-level Addressing Sequen

313595R–DFLASH–11/2012AT45DB041D16. Power-on/Reset StateWhen power is first applied to the device, or when recovering from a reset condition, the devi

323595R–DFLASH–11/2012AT45DB041D18. Electrical SpecificationsTable 18-1. Absolute Maximum Ratings*Temperature under Bias ...

333595R–DFLASH–11/2012AT45DB041DNotes: 1. ICC1during a buffer read is 20mA maximum @ 20MHz.2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guarantee

343595R–DFLASH–11/2012AT45DB041DTable 18-4. AC Characteristics – RapidS/Serial InterfaceSymbol ParameterAT45DB041D(2.5V Version) AT45DB041DMin Typ Max

353595R–DFLASH–11/2012AT45DB041D19. Input Test Waveforms and Measurement LevelstR,tF< 2ns (10% to 90%)20. Output Test Load21. AC WaveformsSix diffe

363595R–DFLASH–11/2012AT45DB041D21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz)21.2 Waveform 2 – SPI Mode 3 Compatible (for Freq

373595R–DFLASH–11/2012AT45DB041D21.5 Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability to operate at higher clock f

383595R–DFLASH–11/2012AT45DB041D21.6 Reset TimingNote: The CS signal should be in the high state before the RESET signal is deasserted.21.7 Command Se

393595R–DFLASH–11/2012AT45DB041D22. Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.22.1 Bu

43595R–DFLASH–11/2012AT45DB041D4. Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels ofgranul

403595R–DFLASH–11/2012AT45DB041D23. Read OperationsThe following block diagram and waveforms illustrate the various read sequences available.23.1 Main

413595R–DFLASH–11/2012AT45DB041D23.3 Buffer Read24. Detailed Bit-level Read Waveform –RapidS Serial Interface Mode 0/Mode 324.1 Continuous Array Read

423595R–DFLASH–11/2012AT45DB041D24.3 Continuous Array Read (Low Frequency: Opcode 03H)24.4 Main Memory Page Read (Opcode: D2H)24.5 Buffer Read (Opcode

433595R–DFLASH–11/2012AT45DB041D24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)24.7 Read Sector Protection Register (Opcode 32H)24.8 Read Sector L

443595R–DFLASH–11/2012AT45DB041D24.9 Read Security Register (Opcode 77H)24.10 Status Register Read (Opcode D7H)24.11 Manufacturer and Device Read (Opc

453595R–DFLASH–11/2012AT45DB041D25. Auto Page Rewrite FlowchartFigure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentiall

463595R–DFLASH–11/2012AT45DB041DFigure 25-2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of a DataFlash secto

473595R–DFLASH–11/2012AT45DB041D26. Ordering Information26.1 Ordering Code DetailNotes: 1. The shipping carrier option is not marked on the devices.2.

483595R–DFLASH–11/2012AT45DB041D27. Packaging Information27.1 8M1-A – MLF (VDFN)TITLE DRAWING NO. GPC REV. Package Drawing Contact:contact@adestotech.

493595R–DFLASH–11/2012AT45DB041D27.2 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE A1 0.10 –

53595R–DFLASH–11/2012AT45DB041D6. Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or from eitherone of the tw

503595R–DFLASH–11/2012AT45DB041D27.3 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected] STN F 8S2, 8-lead, 0.

513595R–DFLASH–11/2012AT45DB041D28. Revision HistoryRevision Level – Revision Date HistoryA – October 2005 Initial ReleaseB – March 2006Added “Prelimi

523595R–DFLASH–11/2012AT45DB041D29. Errata29.1 No Errata ConditionsP – Sept 2009 Pg50: replace package drawing as per the attachedQ – May 2010Changed

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

63595R–DFLASH–11/2012AT45DB041DThe CS pin must remain low during the loading of the opcode, the address bytes, and the read-ing of data. When the end

73595R–DFLASH–11/2012AT45DB041Dmemory is reached, the device will continue reading back at the beginning of the same page. Alow-to-high transition on

83595R–DFLASH–11/2012AT45DB041D7.2 Buffer to Main Memory Page Program with Built-in EraseData written into either buffer 1 or buffer 2 can be programm

93595R–DFLASH–11/2012AT45DB041D7.5 Block EraseA block of eight pages can be erased at one time. This command is useful when large amountsof data has t