Rainbow-electronics AT45DB021D Manual de usuario

Features• Single 2.7V to 3.6V Supply• RapidS Serial Interface: 66MHz Maximum Clock Frequency– SPI Compatible Modes 0 and 3• User Configurable Page Siz

103638K–DFLASH–11/2012AT45DB021D5.8 Main Memory Page Program Through BufferThis operation is a combination of the Buffer Write and Buffer to Main Memo

113638K–DFLASH–11/2012AT45DB021D6.1.2 Disable Sector Protection CommandTo disable the sector protection using the software controlled method, theCS pi

123638K–DFLASH–11/2012AT45DB021DThe table below details the sector protection status for various scenarios of the WP pin, the Enable SectorProtection

133638K–DFLASH–11/2012AT45DB021D7.1.1 Erase Sector Protection Register CommandIn order to modify and change the values of the Sector Protection Regist

143638K–DFLASH–11/2012AT45DB021Dguaranteed. Furthermore, if more than 8-bytes of data is clocked into the device, then the data will wrap backaround t

153638K–DFLASH–11/2012AT45DB021D7.1.4 Various Aspects About the Sector Protection RegisterThe Sector Protection Register is subject to a limit of 10,0

163638K–DFLASH–11/2012AT45DB021D8.1.1 Sector Lockdown RegisterSector Lockdown Register is a nonvolatile register that contains 8-bytes of data, as sho

173638K–DFLASH–11/2012AT45DB021D8.2 Security RegisterThe device contains a specialized Security Register that can be used for purposes such as unique

183638K–DFLASH–11/2012AT45DB021D8.2.2 Reading the Security RegisterThe Security Register can be read by first asserting theCS pin and then clocking in

193638K–DFLASH–11/2012AT45DB021DMain Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to thebuffer an

23638K–DFLASH–11/2012AT45DB021DThe device is optimized for use in many commercial and industrial applications where high-density, low-pin count,low-vo

203638K–DFLASH–11/2012AT45DB021DTable 9-1. Status Register Format10. Deep Power-downAfter initial power-up, the device will default in standby mode. T

213638K–DFLASH–11/2012AT45DB021D11. “Power of 2” Binary Page Size Option“Power of 2” binary page size Configuration Register is a user-programmable no

223638K–DFLASH–11/2012AT45DB021Dtwo bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length,which

233638K–DFLASH–11/2012AT45DB021D12.2 Operation Mode SummaryThe commands described previously can be grouped into four different categories to better d

243638K–DFLASH–11/2012AT45DB021D13. Command TablesTable 13-1. Read CommandsTable 13-2. Program and Erase CommandsTable 13-3. Protection and Security C

253638K–DFLASH–11/2012AT45DB021DTable 13-4. Additional CommandsTable 13-5. Legacy Commands(1)Note: 1. These legacy commands are not recommended for ne

263638K–DFLASH–11/2012AT45DB021DTable 13-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256-Bytes)Note: x = Don’t CarePage Size = 256

273638K–DFLASH–11/2012AT45DB021DTable 13-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (264-Bytes)Note: P = Page Address

283638K–DFLASH–11/2012AT45DB021D14. Power-on/Reset StateWhen power is first applied to the device, or when recovering from a reset condition, the devi

293638K–DFLASH–11/2012AT45DB021Dread operations after reprogramming before the contents could potentially be altered. For example, if the SerialFlash

33638K–DFLASH–11/2012AT45DB021DNotes: 1. The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected toGN

303638K–DFLASH–11/2012AT45DB021DTable 16-2. DC CharacteristicsNotes: 1. ICC1during a buffer read is 20mA maximum @ 20MHz2. All inputs (SI, SCK, CS#, W

313638K–DFLASH–11/2012AT45DB021DTable 16-3. AC Characteristics – RapidS/Serial InterfaceFigure 16-1. Input Test Waveforms and Measurement LevelstR,tF&

323638K–DFLASH–11/2012AT45DB021DFigure 16-2. Output Test Load17. AC WaveformsSix different timing waveforms are shown on page 32. Waveform 1 shows the

333638K–DFLASH–11/2012AT45DB021DFigure 17-3. Waveform 3 – RapidS Mode 0 (FMAX= 66MHz)Figure 17-4. Waveform 4 – RapidS Mode 3 (FMAX= 66MHz)17.1 Utilizi

343638K–DFLASH–11/2012AT45DB021DFigure 17-5. RapidS ModeFigure 17-6. Reset TimingNote: The CS signal should be in the high state before the RESET sign

353638K–DFLASH–11/2012AT45DB021DFigure 17-8. Command Sequence for Read/Write Operations for Page Size 264-Bytes (Except Status RegisterRead, Manufactu

363638K–DFLASH–11/2012AT45DB021DFigure 17-11. Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)18. Read OperationsThe f

373638K–DFLASH–11/2012AT45DB021DFigure 18-2. Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)Figure 18-3. Buffer Read19. De

383638K–DFLASH–11/2012AT45DB021DFigure 19-2. Continuous Array Read (Opcode 0BH)Figure 19-3. Continuous Array Read (Low Frequency: Opcode 03H)Figure 19

393638K–DFLASH–11/2012AT45DB021DFigure 19-5. Buffer Read (Opcode D4H)Figure 19-6. Buffer Read (Low Frequency: Opcode D1H)Figure 19-7. Read Sector Prot

43638K–DFLASH–11/2012AT45DB021D2. Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB021D is divided into three levels of granu

403638K–DFLASH–11/2012AT45DB021DFigure 19-8. Read Sector Lockdown Register (Opcode 35H)Figure 19-9. Read Security Register (Opcode 77H)Figure 19-10. S

413638K–DFLASH–11/2012AT45DB021DFigure 19-11. Manufacturer and Device Read (Opcode 9FH)20. Auto Page Rewrite FlowchartFigure 20-1. Algorithm for Progr

423638K–DFLASH–11/2012AT45DB021DFigure 20-2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of an DataFlash sect

433638K–DFLASH–11/2012AT45DB021D21. Ordering Information21.1 Ordering Code Detail21.2 Green Package Options (Pb/Halide-free/RoHS Compliant)Notes: 1. T

443638K–DFLASH–11/2012AT45DB021D22. Packaging Information22.1 8MA1 – UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] YFG

453638K–DFLASH–11/2012AT45DB021D22.2 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE A1 0.10 –

463638K–DFLASH–11/2012AT45DB021D22.3 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected] STN F 8S2, 8-lead, 0.

473638K–DFLASH–11/2012AT45DB021D23. Revision HistoryDoc. Rev. Date CommentsA 06/2006 Initial release.B 02/2007 Removed RDY/BUSY pin references.C 08/20

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53638K–DFLASH–11/2012AT45DB021D4. Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or from the SRAM data buffe

63638K–DFLASH–11/2012AT45DB021Dboundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of thearray. A l

73638K–DFLASH–11/2012AT45DB021Dread data from the buffer. The D4H opcode can be used at any SCK frequency up to the maximum specified byfCAR1. The D1H

83638K–DFLASH–11/2012AT45DB021D5.4 Page EraseThe Page Erase command can be used to individually erase any page in the main memory array allowing theBu

93638K–DFLASH–11/2012AT45DB021Dthe binary page size (25-bytes), an opcode of 7CH must be loaded into the device, followed by three address bytescompri