Rainbow-electronics AT45DB041E Manual de usuario

8783B–DFLASH–11/2012Features Single 1.65V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Supports RapidS™

10AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20126. Program and Erase Commands6.1 Buffer WriteUtilizing the Buffer Write command allows data clock

11AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012When a low-to-high transition occurs on the CS pin, the device will program the data stored in th

12AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012buffer is reached, then the device will wrap around back to the beginning of the buffer. When usi

13AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20126.7 Page EraseThe Page Erase command can be used to individually erase any page in the main memor

14AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20126.9 Sector EraseThe Sector Erase command can be used to individually erase any sector in the main

15AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012The device also incorporates an intelligent algorithm that can detect when a byte location fails

16AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 6-4. Operations Allowed and Not Allowed During SuspendCommandOperation During Program Suspe

17AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20126.12 Program/Erase ResumeThe Program/Erase Resume command allows a suspended program or erase ope

18AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20127. Sector ProtectionTwo protection methods, hardware and software controlled, are provided for pr

19AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 7-2. Disable Sector Protection 7.2 Hardware Controlled ProtectionSectors specified for pro

2AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012DescriptionThe AT45DB041E is a 1.65V minimum, serial-interface sequential access Flash memory idea

20AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20127.3 Sector Protection RegisterThe nonvolatile Sector Protection Register specifies which sectors

21AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 7-4. Erase Sector Protection Register 7.3.2 Program Sector Protection Register Once the Se

22AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20127.3.3 Read Sector Protection RegisterTo read the Sector Protection Register, an opcode of 32h and

23AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20128. Security Features8.1 Sector LockdownThe device incorporates a sector lockdown mechanism that a

24AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte ValueTable 8-4. Read Sector Lockdow

25AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20128.2 Security RegisterThe device contains a specialized Security Register that can be used for pur

26AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20128.2.2 Reading the Security RegisterTo read the Security Register, an opcode of 77h and three dumm

27AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20129. Additional Commands 9.1 Main Memory Page to Buffer TransferA page of data can be transferred f

28AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012To initiate an Auto Page Rewrite with the a binary page size (256 bytes), the opcode 58H for Buff

29AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 9-2. Status Register Format – Byte 2Note: 1. R = Readable only9.4.1 RDY/BUSY BitThe RDY/BUS

3AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 1-1. Pin ConfigurationsSymbol Name and FunctionAsserted StateTypeCSChip Select: Asserting th

30AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20129.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed success

31AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201210. Deep Power-DownDuring normal operation, the device will be placed in the standby mode to cons

32AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201210.1 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume normal devic

33AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201210.2 Ultra-Deep Power-DownThe Ultra-Deep Power-Down mode allows the device to consume far less po

34AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201210.2.1 Exit Ultra-Deep Power-DownTo exit from the Ultra-Deep Power-Down mode, the CS pin must sim

35AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201211. Buffer and Page Size ConfigurationThe memory array of DataFlash devices is actually larger th

36AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201212. Manufacturer and Device ID ReadIdentification information can be read from the device to enab

37AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 12-3. EDI DataFigure 12-1. Read Manufacturer and Device IDByte Number Bit 7 Bit 6 Bit 5 Bit

38AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201213. Software ResetIn some applications, it may be necessary to prematurely terminate a program or

39AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201214. Operation Mode SummaryThe commands described previously can be grouped into four different ca

4AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20122. Block DiagramFigure 2-1. Block DiagramFlash Memory ArrayI/O InterfaceSCKCSRESETVCCGNDWPSOSIPage

40AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201215. Command TablesTable 15-1. Read CommandsTable 15-2. Program and Erase CommandsCommand OpcodeMa

41AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 15-3. Protection and Security CommandsTable 15-4. Additional CommandsTable 15-5. Legacy Com

42AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256 bytes)Note: 1. Shown

43AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Table 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (264 bytes)No

44AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201216. Power-On/Reset StateWhen power is first applied to the device, or when recovering from a rese

45AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201217. System ConsiderationsThe serial interface is controlled by the Serial Clock (SCK), Serial Inp

46AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201218. Electrical Specifications18.1 Absolute Maximum Ratings*18.2 DC and AC Operating RangeTemperat

47AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201218.3 DC Characteristics Notes: 1. Typical values measured at 3.0V at 25C.2. ICC2 during a Buffer

48AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201218.4 AC CharacteristicsNote: 1. Values are based on device characterization, not 100% tested in p

49AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201218.5 Program and Erase CharacteristicsNotes: 1. Values are based on device characterization, not

5AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20123. Memory ArrayTo provide optimal flexibility, the AT45DB041E memory array is divided into three l

50AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201221. Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability to opera

51AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 21-2. Command Sequence for Read/Write Operations for Page Size 256 bytes (Except Status Re

52AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201222. AC WaveformsFour different timing waveforms are shown in Figure 22-1 through Figure 22-4. Wav

53AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 22-3. Waveform 3 = RapidS Mode 0Figure 22-4. Waveform 4 = RapidS Mode 3CSSCKSISOtCSSValid

54AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201223. Write OperationsThe following block diagram and waveforms illustrate the various write sequen

55AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201224. Read OperationsThe following block diagram and waveforms illustrate the various read sequence

56AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 24-3. Main Memory Page to Buffer TransferData From the selected Flash Page is read into ei

57AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201225. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3Figure 25-1. Continuous Array Read (Le

58AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 25-4. Main Memory Page Read (Opcode D2h)Figure 25-5. Buffer Read (Opcode D4h or D6h)Figure

59AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 25-7. Read Sector Protection Register (Opcode 32h)Figure 25-8. Read Sector Lockdown Regist

6AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20124. Device OperationThe device operation is controlled by instructions from the host processor. The

60AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 25-10. Status Register Read (Opcode D7h)Figure 25-11. Manufacturer and Device Read (Opcode

61AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201226. Auto Page Rewrite FlowchartFigure 26-1. Algorithm for Programming or Re-programming of the En

62AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array RandomlyNotes: 1. To

63AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201227. Ordering Information (Standard DataFlash Page Size)27.1 Ordering DetailDevice GradeH = Gree

64AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201227.2 Ordering Codes (Standard DataFlash Page Size)Notes: 1. The shipping carrier suffix is not ma

65AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201227.3 Ordering Codes (Binary Page Size)Notes: 1. The shipping carrier suffix is not marked on the

66AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201228. Packaging Information28.1 8S1 – 8-lead JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS

67AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201228.2 8S2 – 8-lead EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:contact@adestotech.

68AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201228.3 8MA1 – 8-pad UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected] Y

69AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201228.4 9CC1 – 9-ball UBGADRAWING NO. REV. GPCTITLEPackage Drawing Contact:[email protected]

7AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/20125. Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or fro

70AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/201229. Revision HistoryDoc. Rev. Date Comments8783B 11/2012Add Legacy Commands table.Update to Adest

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8AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012A low-to-high transition on the CS pin will terminate the read operation and tri-state the output

9AT45DB041E [ADVANCE DATASHEET]8783B–DFLASH–11/2012of the main memory array to read and the last 9 bits (BA8 - BA0) of the 20-bit address sequence sp