Rainbow-electronics ATA6630 Manual de usuario

Features• Master and Slave Operation Possible• Supply Voltage up to 40V• Operating voltage VS = 5V to 27V• Typically 10 µA Supply Current During Sleep

109117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] A falling edge at the LIN pin followed by a dominant bus level maintained for a certain timeperiod (tb

119117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]4.3 Sleep ModeA falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has

129117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] A falling edge at the LIN pin followed by a dominant bus level maintained for a certain timeperiod (tb

139117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]4.4 Sleep or Silent Mode: Behavior at a Floating LIN-bus or a Short Circuited LIN to GNDIn Sleep or in

149117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] Figure 4-7. Short Circuit to GND on the LIN bus During Sleep- or Silent Mode Sleep/Silent ModeIVSsleep

159117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]4.5 Fail-safe ModeThe device automatically switches to Fail-safe Mode at system power-up. The voltage r

169117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 4.6 Unpowered ModeIf you connect battery voltage to the application circuit, the voltage at the VS pin

179117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]5. Wake-up Scenarios from Silent or Sleep Mode5.1 Remote Wake-up via Dominant Bus StateA voltage less t

189117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 5.5 Fail-safe Features• During a short-circuit at LIN to VBattery, the output limits the output curren

199117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]5.6 Voltage RegulatorThe voltage regulator needs an external capacitor for compensation and for smoothi

29117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] Figure 1-1. Block Diagram HighSpeedModeAdjustableWatchdogOscillatorShort Circuit andOvertemperatureProt

209117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 6. WatchdogThe watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative e

219117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]Figure 6-1. Timing Sequence with RWD_OSC = 51 kΩ 6.2 Worst Case Calculation with RWD_OSC = 51 kΩThe int

229117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 7. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause per

239117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]8. Thermal CharacteristicsParameters Symbol Min. Typ. Max. UnitThermal resistance junction to heat slug

249117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 2 RXD Output Pin2.1Low-level output sink currentNormal ModeVLIN=0VVRXD=0.4VRXD IRXD1.3 2.5 8 mA A2.2 L

259117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]8.3 Driver dominant voltageVVS = 18VRload = 500 ΩLIN V_HiSUP2VA8.4 Driver dominant voltageVVS = 7.0VRlo

269117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 10.2Time delay for mode change from Fail-safe into Normal Mode via EN pinVEN = VCCEN tnorm51520µsA10.3

279117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]12 NRES Open Drain Output Pin12.1 Low-level output voltageVS≥ 5.5VINRES = 1 mAINRES = 250 µANRES VNRESL

289117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 17 VCC Voltage Regulator ATA6628 in Normal/Fail-safe and Silent Mode, VCC and PVCC Short-circuited17.1

299117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]19 DIV_ON Input Pin19.1 Low-level voltage input DIV_ON VDIV_ON–0.3 +0.8 V A19.2 High-level voltage inpu

39117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]2. Pin ConfigurationFigure 2-1. Pinning QFN20 67 8 10920 19 18QFN 5 mm 5 mm0.65 mm pitch20 leadATA6628

309117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] Figure 9-1. Definition of Bus Timing Characteristics TXD(Input to transmitting node)VS(Transceiver sup

319117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]Figure 9-2. Application Circuit 67 8 10920 19 18MLP 5 mm 5 mm0.65 mm pitch20 leadATA6628ATA6630161112

329117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 11. Package Information10. Ordering InformationExtended Type Number Package RemarksATA6628-PGPW QFN20

339117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]12. Revision HistoryPlease note that the following page numbers referred to in this section refer to th

9117C–AUTO–10/09Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel Asia

49117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 3. Functional Description3.1 Physical Layer CompatibilitySince the LIN physical layer is independent fr

59117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]3.7 Input/Output Pin (TXD)In Normal Mode the TXD pin is the microcontroller interface used to control th

69117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 3.13 TM Input PinThe TM pin is used for final production measurements at Atmel®. In normal application,

79117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]3.20 DIV_ON Input PinThe DIV_ON pin is a low voltage input. It is used to switch on or off the internal

89117C–AUTO–10/09ATA6628/ATA6630 [Preliminary] 4. Modes of OperationFigure 4-1. Modes of Operation Unpowered Mode(See Section 4.5)a: VS > VSthFb: V

99117C–AUTO–10/09ATA6628/ATA6630 [Preliminary]4.1 Normal ModeThis is the normal transmitting and receiving mode. The voltage regulator is active and c