1Features• Compatible with MCS-51™ Products• 8K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Oper
AT89C5210Baud Rate GeneratorTimer 2 is selected as the baud rate generator by settingTCLK and/or RCLK in T2CON (Table 2). Note that thebaud rates for
AT89C5211Programmable Clock OutA 50% duty cycle clock can be programmed to come out onP1.0, as shown in Figure 5. This pin, besides being a regu-lar I
AT89C5212Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use as
AT89C5213Program Memory Lock Bits The AT89C52 has three lock bits that can be left unpro-grammed (U) or can be programmed (P) to obtain theadditional
AT89C5214Reading the Signature Bytes The signature bytes areread by the same procedure as a normal verification oflocations 030H, 031H, and 032H, exce
AT89C5215Figure 9. Programming the Flash Memory Figure 10. Verifying the Flash MemoryNote: 1. Only used in 12-volt programming mode.P1P2.6P3.6P2.0 -
AT89C5216Flash Programming and Verification Waveforms - High-voltage Mode (VPP=12V)Flash Programming and Verification Waveforms - Low-voltage Mode (VP
AT89C5217Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL
AT89C5218AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all otheroutput
AT89C5219External Program Memory Read CycleExternal Data Memory Read CycletLHLLtLLIVtPLIVtLLAXtPXIZtPLPHtPLAZtPXAVtAVLLtLLPLtAVIVtPXIXALEPSENPORT 0POR
AT89C522Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7QUICKFLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDPTRRAM ADDR.R
AT89C5220External Data Memory Write CycleExternal Clock Drive WaveformstLHLLtLLWLtLLAXtWHLHtAVLLtWLWHtAVWLtQVWXtQVWHtWHQXA0 - A7 FROM RI OR DPLA
AT89C5221.Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a log
AT89C5222Ordering InformationSpeed(MHz)PowerSupply Ordering Code Package Operation Range12 5V ± 20% AT89C52-12ACAT89C52-12JCAT89C52-12PCAT89C52-12QC44
AT89C5223Packaging InformationControlling dimension: millimeters1.20(0.047) MAX10.10(0.394)9.90(0.386)SQ12.21(0.478)11.75(0.458)SQ0.75(0.030)0.45(0.01
© Atmel Corporation 1999.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa
AT89C523The AT89C52 provides the following standard features: 8Kbytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bittimer/counters, a six-vect
AT89C524timing or clocking purposes. Note, however, that one ALEpulse is skipped during each access to external datamemory. If desired, ALE operation
AT89C525Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table 1.Note that not
AT89C526Instructions that use indirect addressing access the upper128 bytes of RAM. For example, the following indirectaddressing instruction, where R
AT89C527Figure 1. Timer in Capture ModeFigure 2 shows Timer 2 automatically counting up whenDCEN = 0. In this mode, two options are selected by bitEX
AT89C528Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)Table 4. T2MOD – Timer 2 Mode Control RegisterT2MOD Address = 0C9H Reset Value = XXXX XX00BNot
AT89C529Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)Figure 4. Timer 2 in Baud Rate Generator ModeOSCEXF2TF2T2EX PINCOUNTDIRECTION1=UP0=DOWNT2 PIN
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