Rainbow-electronics AT89C55WD Manual de usuario

1Features• Compatible with MCS®-51 Products• 20K Bytes of Reprogrammable Flash Memory• Endurance: 1000 Write/Erase Cycles• 4V to 5.5V Operating Range•

10AT89C55WD1921B–MICRO–09/02HardwareWatchdogTimer(One-timeEnabled withReset-out)The WDT is intended as a recovery method in situations where the CPU m

11AT89C55WD1921B–MICRO–09/02Timer 0 and 1 Timer 0 and Timer 1 in the AT89C55WD operate the same way as Timer 0 and Timer 1 in theAT89C51 and AT89C52.T

12AT89C55WD1921B–MICRO–09/02Figure 5. Timer in Capture ModeFigure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two optionsare

13AT89C55WD1921B–MICRO–09/02Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)Table 6 . T2MOD – Timer 2 Mode Control RegisterT2MOD Address = 0C9H Reset Val

14AT89C55WD1921B–MICRO–09/02Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)Figure 8. Timer 2 in Baud Rate Generator ModeOSCEXF2TF2T2EX PINCOUNTDIRECTIO

15AT89C55WD1921B–MICRO–09/02Baud RateGeneratorTimer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table2). Note that

16AT89C55WD1921B–MICRO–09/02Figure 9. Timer 2 in Clock-Out ModeOSCEXF2P1.0(T2)P1.1(T2EX)TR2EXEN2C/T2 BITTRANSITIONDETECTORTIMER 2INTERRUPTT2OE (T2M

17AT89C55WD1921B–MICRO–09/02ProgrammableClock OutA 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 9. Thispin, besides

18AT89C55WD1921B–MICRO–09/02Figure 10. Interrupt SourcesTable 7 . Interrupt Enable (IE) Register(MSB) (LSB)EA– ET2 ES ET1 EX1 ET0 EX0Enable Bit = 1 en

19AT89C55WD1921B–MICRO–09/02OscillatorCharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can beconf

2AT89C55WD1921B–MICRO–09/02Pin ConfigurationsTQFPPDIPPLCC12345678910113332313029282726252423P1.5P1.6P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0) P3.2(INT1) P3.

20AT89C55WD1921B–MICRO–09/02Figure 12. External Clock Drive ConfigurationXTAL2XTAL1GNDNCEXTERNALOSCILLATORSIGNALTable 8 . Status of External Pins Duri

21AT89C55WD1921B–MICRO–09/02ProgramMemory LockBitsThe AT89C55WD has three lock bits that can be left unprogrammed (U) or can be pro-grammed (P) to obt

22AT89C55WD1921B–MICRO–09/02puts,andthenextcyclemaybegin.DataPolling may begin any time after a write cycle hasbeen initiated.Ready/Busy: The progress

23AT89C55WD1921B–MICRO–09/02ProgrammingInterfaceEvery code byte in the Flash array can be programmed by using the appropriate combinationof control si

24AT89C55WD1921B–MICRO–09/02Figure 13. Programming the Flash MemoryFigure 14. Verifying the Flash MemoryNote: *Programming address line A14 (P3.4) is

25AT89C55WD1921B–MICRO–09/02Flash Programming and Verification CharacteristicsTA=20°Cto30°C, VCC=4.5Vto5.5VSymbol Parameter Min Max UnitsVPPProgrammin

26AT89C55WD1921B–MICRO–09/02Flash Programming and Verification WaveformsLock Bit ProgrammingtGLGHtGHSLtAVGLtSHGLtDVGLtGHAXtAVQVtGHDXtEHSHtELQVtWCBUSYR

27AT89C55WD1921B–MICRO–09/02Parallel Chip Erase Mode10 msTest ConditionsSetupTest Conditions SetupALE/PROGP3<0>EraseDCEraseEraseVCC = 4.5V to 5.

28AT89C55WD1921B–MICRO–09/02Notes: 1. Under steady state (non-transient) conditions, IOLmust be externally limited as follows:Maximum IOLperportpin:10

29AT89C55WD1921B–MICRO–09/02ACCharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN =100pF;load capacitance for a

3AT89C55WD1921B–MICRO–09/02Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7QUICKFLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCO

30AT89C55WD1921B–MICRO–09/02External Program Memory Read CycleExternal Data Memory Read CycletLHLLtLLIVtPLIVtLLAXtPXIZtPLPHtPLAZtPXAVtAVLLtLLPLtAVIVtP

31AT89C55WD1921B–MICRO–09/02External Data Memory Write CycleExternal Clock Drive WaveformstLHLLtLLWLtLLAXtWHLHtAVLLtWLWHtAVWLtQVWXtQVWHtWHQXA0 - A7

32AT89C55WD1921B–MICRO–09/02Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VC

33AT89C55WD1921B–MICRO–09/02Ordering InformationSpeed(MHz)PowerSupply Ordering Code Package Operation Range24 4.0V to 5.5V AT89C55WD-24ACAT89C55WD-24J

34AT89C55WD1921B–MICRO–09/02Package Information44A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 mm Bo

35AT89C55WD1921B–MICRO–09/0244J–PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mo

36AT89C55WD1921B–MICRO–09/0240P6 – PDIP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 40P6, 40-lead (0.600"/15.24 mm Wide) Pla

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

4AT89C55WD1921B–MICRO–09/02Pin DescriptionVCC Supply voltage.GND Ground.Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output por

5AT89C55WD1921B–MICRO–09/02RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets thedevice. This pin drive

6AT89C55WD1921B–MICRO–09/02SpecialFunctionRegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shownin Table

7AT89C55WD1921B–MICRO–09/02Interrupt Registers: The individual interrupt enable bits are in the IE register. Two prioritiescan be set for each of the

8AT89C55WD1921B–MICRO–09/02Table 4 . AUXR1: Auxiliary Register 1AUXR1 Address = A2H Reset Value = XXXXXXX0BNot Bit Addressable––– – – – –DPSBit 7 6 5

9AT89C55WD1921B–MICRO–09/02MemoryOrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to64 Kbytes each of external