Features•16 Channel GPS Correlator– 8192 Search Bins with GPS Acquisition Accelerator– Accuracy: 2.5m CEP (Stand-Alone, S/A off)– Time to First Fix: 3

104890AS–GPS–09/05ATR0621 [Preliminary] 3.3 Setting GPSMODE0 to GPSMODE12The start-up configuration of a ROM-based system without external non-volat

114890AS–GPS–09/05 ATR0621 [Preliminary] 3.3.3 Serial I/O ConfigurationThe ATR0621 features a two-stage I/O message and protocol selection procedure

124890AS–GPS–09/05ATR0621 [Preliminary] The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM-Defaults):3.

134890AS–GPS–09/05 ATR0621 [Preliminary] 3.3.5 Active Antenna SupervisorIf GPSMODE configuration is enabled, the two pins P0/NANTSHORT and P15/ANTON,

144890AS–GPS–09/05ATR0621 [Preliminary] The Antenna Supervisor Software will be configured as follows:1. Enable Control Signal2. Enable Short Circui

154890AS–GPS–09/05 ATR0621 [Preliminary] Table 3-15. Recommended Pin Connection Pin Name Recommended External CircuitP0/NANTSHORT Internal pull-down

164890AS–GPS–09/05ATR0621 [Preliminary] P19/SIGLO2/GPSMODE6Pull-up resistor to VDD18 or pull-down resistor to GND if used as input by user applicati

174890AS–GPS–09/05 ATR0621 [Preliminary] 4. OscillatorFigure 4-1. Crystal Connection 32 kHzCrystalOscillatorXT_INXT_OUTATR0621 internal32.768 kHz clo

184890AS–GPS–09/05ATR0621 [Preliminary] 6. Power ConsumptionMode Conditions Typ. UnitSleep At 1.8V, no CLK23 0.065(1)mAShutdown RTC and backup SRAM

194890AS–GPS–09/05 ATR0621 [Preliminary] 9. Package LFBGA100 8. Ordering InformationExtended Type Number Package RemarksATR0621-7FQY LFBGA100 9 mm ×

24890AS–GPS–09/05ATR0621 [Preliminary] 1. DescriptionThe GPS baseband processor ATR0621 includes a 16-channel GPS correlator and is based on the ARM

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34890AS–GPS–09/05 ATR0621 [Preliminary] Figure 1-1. Block Diagram Embedded ICEInterface toOff-ChipMemory(EBI)SRAM128KROM384KBRIDGEJTAGASBPDC2USB USAR

44890AS–GPS–09/05ATR0621 [Preliminary] 2. Architectural Overview2.1 DescriptionThe ATR0621 architecture consists of two main buses, the Advanced Sys

54890AS–GPS–09/05 ATR0621 [Preliminary] 3. Pin Configuration3.1 PinoutFigure 3-1. Pinout LFBGA100 (Top View) ATR062112345678910ABCDEFGHJKTable 3-1. A

64890AS–GPS–09/05ATR0621 [Preliminary] EM_A18 B3 OUTEM_A19 C5 OUTEM_DA0 B6 I/O PDEM_DA1 B10 I/O PDEM_DA2 C7 I/O PDEM_DA3 C10 I/O PDEM_DA4 D10 I/O PD

74890AS–GPS–09/05 ATR0621 [Preliminary] P6 A8 I/O OH NOE/NRD NOE/NRD “0”P7 D2 I/O OH NUB/NWR1 NUB/NWR1 “0”P8 G2 I/O STATUSLED “0”P9 J8 I/O PU EXTINT0

84890AS–GPS–09/05ATR0621 [Preliminary] 3.2 Signal DescriptionVBAT18 G6 OUTVDD18 E6 INVDD18 F7 INVDD18 F6 INVDDIO(2)E5 INVDD_USB(3)F5 INXT_IN J9 INXT

94890AS–GPS–09/05 ATR0621 [Preliminary] SPISCK SPI Clock I/O – PIO-controlled after resetMOSI Master Out Slave In I/O – PIO-controlled after resetMIS